| 1 |
/* RCSid: $Id: tardev.h,v 1.3 2003/02/22 02:07:28 greg Exp $ */ |
| 2 |
/* |
| 3 |
* Board types used for targa->boardType |
| 4 |
*/ |
| 5 |
#ifndef _RAD_TARDEV_H_ |
| 6 |
#define _RAD_TARDEV_H_ |
| 7 |
|
| 8 |
#ifdef __cplusplus |
| 9 |
extern "C" { |
| 10 |
#endif |
| 11 |
|
| 12 |
#define TYPE_8 8 |
| 13 |
#define TYPE_16 16 |
| 14 |
#define TYPE_24 24 |
| 15 |
#define TYPE_32 32 |
| 16 |
#define TYPE_M8 -8 |
| 17 |
|
| 18 |
/* |
| 19 |
* TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel |
| 20 |
*/ |
| 21 |
|
| 22 |
#define XMIN 0 |
| 23 |
#define YMIN 0 |
| 24 |
#define XMAX 512 /* maximum X value */ |
| 25 |
#define YMAX 512 /* maximum Y value */ |
| 26 |
#define XRES 512 /* X resolution */ |
| 27 |
#define YRES 512 /* Y Resolution */ |
| 28 |
#define YVISMAX (2*targa->LinesPerField) /* Maximum visible Y coordinate */ |
| 29 |
#define YVISMIN 0 /* Minimum visible Y coordiate */ |
| 30 |
#define DEF_ROWS 400 /* Default number of rows */ |
| 31 |
|
| 32 |
|
| 33 |
#define DEF_IOBASE 0x220 |
| 34 |
#define IOBASE targa->iobase /* io base location of graphics registers */ |
| 35 |
#define MEMSEG targa->memloc /* use the variable so we can use */ |
| 36 |
#define SCNSEG targa->memloc /* the one defined in TARGA */ |
| 37 |
#define SRCBANK (targa->memloc+0x0800) /* use high-bank as source bank */ |
| 38 |
#define DESTBANK targa->memloc /* use lo-bank as destination bank */ |
| 39 |
#define DEF_MEMSEG 0xa000 /* Default screen memory */ |
| 40 |
|
| 41 |
/* |
| 42 |
* Output register definitions |
| 43 |
*/ |
| 44 |
#define MODEREG (IOBASE+0xC00) /* Mode Register address */ |
| 45 |
#define MASKREG (IOBASE+0x800) /* Mask Registers */ |
| 46 |
#define UNDERREG (IOBASE+0x800) /* Underscan register */ |
| 47 |
#define OVERREG (IOBASE+0x802) /* overscan register */ |
| 48 |
#define DESTREG (IOBASE+0x802) /* Address of Page Select Lower Register */ |
| 49 |
#define SRCREG (IOBASE+0x803) /* Address of Page Select Upper Register */ |
| 50 |
#define VCRCON (IOBASE+0x400) /* Address of Contrast/VidSrc Register */ |
| 51 |
#define BLNDREG VCRCON |
| 52 |
#define SATHUE (IOBASE+0x402) /* Satuation/Hue Register address */ |
| 53 |
#define DRREG (IOBASE+0x401) /* ADDRESS OF Controller Write Register */ |
| 54 |
#define VERTPAN (IOBASE+0x403) /* Address of Vertical Pan Register */ |
| 55 |
#define BORDER (IOBASE) /* Address of Page Select Lower Register */ |
| 56 |
|
| 57 |
|
| 58 |
/* |
| 59 |
* Input register definitions |
| 60 |
*/ |
| 61 |
#define VIDEOSTATUS (IOBASE+0xC02) /* Video Status Register */ |
| 62 |
#define RASTERREG (IOBASE+0xC00) /* Raster counter register */ |
| 63 |
|
| 64 |
|
| 65 |
|
| 66 |
/* |
| 67 |
* Default register values |
| 68 |
*/ |
| 69 |
#define DEF_MODE 1 /* Default mode register value */ |
| 70 |
/* Memory selected, 512x512, 1x */ |
| 71 |
/* Display mode */ |
| 72 |
#define DEF_MASK 0 /* default memory mask */ |
| 73 |
#define DEF_SATURATION 0x4 /* default saturation value */ |
| 74 |
#define DEF_HUE 0x10 /* default hue value */ |
| 75 |
#define DEF_CONTRAST 0x10 /* default contrast value */ |
| 76 |
#define DEF_VIDSRC 0 /* default video source value - Composite */ |
| 77 |
#define DEF_VERTPAN 56 /* assumes 400-line output */ |
| 78 |
#define DEF_BORDER 0 /* default border color */ |
| 79 |
|
| 80 |
|
| 81 |
/* |
| 82 |
* MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS |
| 83 |
*/ |
| 84 |
/* |
| 85 |
* ****************************************************** |
| 86 |
* MODE REGISTERS |
| 87 |
* ****************************************************** |
| 88 |
*/ |
| 89 |
#define MSK_MSEL 0xfffC /* memory select bits */ |
| 90 |
#define SHF_MSEL 0x0000 |
| 91 |
#define MSEL 1 |
| 92 |
|
| 93 |
#define MSK_IBIT 0xfffb /* Interlace bit */ |
| 94 |
#define SHF_IBIT 2 |
| 95 |
|
| 96 |
#define MSK_RES 0xFFC7 /* disp. resolution and screen select bits */ |
| 97 |
#define SHF_RES 3 |
| 98 |
#define S0_512X512_0 0 /* 512x512 resolution screen */ |
| 99 |
#define S1_512X512_1 1 |
| 100 |
#define S2_512X256_0 2 /* 512x256 resolution screen 0 */ |
| 101 |
#define S3_512X256_1 3 /* 512x256 resolution screen 1 */ |
| 102 |
#define S4_256X256_0 4 /* 256x256 resolution screen 0 */ |
| 103 |
#define S5_256X256_1 5 /* .... */ |
| 104 |
#define S6_256X256_2 6 |
| 105 |
#define S7_256X256_3 7 |
| 106 |
|
| 107 |
#define MSK_REGWRITE 0xFFBF /* mask for display register write */ |
| 108 |
#define SHF_REGWRITE 6 |
| 109 |
#define REGINDEX 0 /* to write an index value */ |
| 110 |
#define REGVALUE 1 /* to write a value */ |
| 111 |
|
| 112 |
#define MSK_BIT9 0xFF7F /* maks for high-order bit of DR's */ |
| 113 |
#define SHF_BIT9 7 |
| 114 |
|
| 115 |
#define MSK_TAPBITS 0xFCFF /* mask for setting the tap bits */ |
| 116 |
#define SHF_TAPBITS 8 |
| 117 |
|
| 118 |
#define MSK_ZOOM 0xF3FF /* Mask for zoom factor */ |
| 119 |
#define SHF_ZOOM 10 |
| 120 |
|
| 121 |
#define MSK_DISPLAY 0xCFFF /* Mask for display mode */ |
| 122 |
#define SHF_DISPLAY 12 |
| 123 |
#define MEMORY_MODE 0 |
| 124 |
#define LIVE_FIXED 1 |
| 125 |
#define OVERLAY_MODE 2 |
| 126 |
#define LIVE_LIVE 3 |
| 127 |
#define DEF_DISPLAY 0 |
| 128 |
|
| 129 |
#define MSK_CAPTURE 0xBFFF /* Mask for capture bit */ |
| 130 |
#define SHF_CAPTURE 14 |
| 131 |
|
| 132 |
#define MSK_GENLOCK 0x7FFF /* MASK FOR GENLOCK */ |
| 133 |
#define SHF_GENLOCK 15 |
| 134 |
#define DEF_GENLOCK 0 |
| 135 |
/* |
| 136 |
* Video status input register |
| 137 |
*/ |
| 138 |
#define FIELDBIT 0x0001 |
| 139 |
#define VIDEOLOSS 0x0002 |
| 140 |
/* |
| 141 |
* VIDEO SOURCE/CONTROL REGISTER |
| 142 |
*/ |
| 143 |
#define MSK_CONTRAST 0xFFC1 |
| 144 |
#define SHF_CONTRAST 1 |
| 145 |
#define MAX_CONTRAST 0x1f |
| 146 |
|
| 147 |
#define MSK_RGBORCV 0xBF |
| 148 |
#define SHF_RGBORCV 6 |
| 149 |
#define RGB 1 |
| 150 |
#define CV 0 |
| 151 |
|
| 152 |
#define MSK_VCRORCAMERA 0x7F |
| 153 |
#define SHF_VCRORCAMERA 7 |
| 154 |
#define VCR 1 |
| 155 |
#define CAMERA 0 |
| 156 |
|
| 157 |
/* |
| 158 |
* HUE/SATUATION REGISTER |
| 159 |
*/ |
| 160 |
#define MSK_HUE 0xE0 |
| 161 |
#define SHF_HUE 0 |
| 162 |
#define MAX_HUE 0x1f |
| 163 |
|
| 164 |
#define MSK_SATURATION 0x1F |
| 165 |
#define SHF_SATURATION 5 |
| 166 |
#define MAX_SATURATION 0x07 |
| 167 |
|
| 168 |
|
| 169 |
/* |
| 170 |
* ********************************************* |
| 171 |
* Display register settings |
| 172 |
* ********************************************* |
| 173 |
* |
| 174 |
* Screen Positioning Registers: |
| 175 |
* DR 0-3 |
| 176 |
*/ |
| 177 |
#define LEFTBORDER 0 |
| 178 |
#define DEF_LEFT 85 |
| 179 |
#define MIN_LEFT 75 |
| 180 |
#define MAX_LEFT 95 |
| 181 |
#define RIGHTBORDER 1 |
| 182 |
#define DEF_RIGHT (DEF_LEFT+256) |
| 183 |
#define TOPBORDER 2 |
| 184 |
#define DEF_TOP 40 |
| 185 |
#define MIN_TOP 20 |
| 186 |
#define BOTTOMBORDER 3 |
| 187 |
#define DEF_BOTTOM (DEFTOP+DEFROWS/2) |
| 188 |
#define MAX_BOTTOM 261 |
| 189 |
|
| 190 |
/* |
| 191 |
* REgisters which track 0-3 |
| 192 |
*/ |
| 193 |
#define DR8 8 |
| 194 |
#define PRESHIFT DR8 |
| 195 |
#define EQU_DR8 DR0 |
| 196 |
#define DR9 9 |
| 197 |
#define EQU_DR9 DR1 |
| 198 |
#define DR10 10 |
| 199 |
#define EQU_DR10 DR2 |
| 200 |
#define DR11 11 |
| 201 |
#define EQU_DR11 DR3 |
| 202 |
|
| 203 |
/* |
| 204 |
* REQUIRED REGISTERS |
| 205 |
*/ |
| 206 |
#define DR4 4 |
| 207 |
#define DEF_DR4 352 |
| 208 |
#define DR5 5 |
| 209 |
#define DEF_DR5 1 |
| 210 |
#define DR6 6 |
| 211 |
#define DEF_DR6 0 |
| 212 |
#define DR7 7 |
| 213 |
#define DEF_DR7 511 |
| 214 |
#define DR12 12 |
| 215 |
#define DEF_DR12 20 |
| 216 |
#define DR13 13 |
| 217 |
#define DEF_DR13 22 |
| 218 |
#define DR14 14 |
| 219 |
#define DEF_DR14 0 |
| 220 |
#define DR15 15 |
| 221 |
#define DEF_DR15 511 |
| 222 |
#define DR16 16 |
| 223 |
#define DEF_DR16 0 |
| 224 |
#define DR17 17 |
| 225 |
#define DEF_DR17 0 |
| 226 |
#define DR18 18 |
| 227 |
#define DEF_DR18 0 |
| 228 |
#define DR19 19 |
| 229 |
#define DEF_DR19 4 |
| 230 |
|
| 231 |
/* interlace mode register & parameters */ |
| 232 |
#define DR20 20 |
| 233 |
#define INTREG 0x14 |
| 234 |
#define DEF_INT 0 /* default to interlace mode 0 */ |
| 235 |
#define MSK_INTERLACE 0x0003 |
| 236 |
|
| 237 |
|
| 238 |
|
| 239 |
struct TARStruct { |
| 240 |
/* Board Configuration */ |
| 241 |
int memloc; /* memory segment */ |
| 242 |
int iobase; /* IOBASE segment */ |
| 243 |
int BytesPerPixel; /* number of words per pixel */ |
| 244 |
int RowsPerBank; /* number of row per 64K bank */ |
| 245 |
int MaxBanks; /* maximum bank id */ |
| 246 |
int AddressShift; /* number of bits to shift address */ |
| 247 |
|
| 248 |
/* Control registers */ |
| 249 |
int mode; /* mode register */ |
| 250 |
int Mask; /* mask register */ |
| 251 |
int PageMode; /* current page mode (screen res. and page) */ |
| 252 |
unsigned PageLower; /* Lower Page Select register */ |
| 253 |
unsigned PageUpper; /* upper Page select register */ |
| 254 |
int VCRCon; /* VCRContract register */ |
| 255 |
int SatHue; /* Hue and Saturation register */ |
| 256 |
long BorderColor; /* Border color register */ |
| 257 |
int VertShift; /* Vertical Pan Register */ |
| 258 |
|
| 259 |
int PanXOrig, PanYOrig; /* x,y pan origin */ |
| 260 |
|
| 261 |
/* TARGA-SET PARAMETERS */ |
| 262 |
int boardType; /* See TYPE_XX IN THIS FILE */ |
| 263 |
/* FOR DEFINITION OF Board Types */ |
| 264 |
int xOffset; /* X-offset */ |
| 265 |
int yOffset; /* Y-Offset */ |
| 266 |
int LinesPerField; /* maximum visible row count */ |
| 267 |
int InterlaceMode; /* desired interlace mode */ |
| 268 |
int AlwaysGenLock; /* Genlock always on or not */ |
| 269 |
int Contrast; /* Desired Contrast */ |
| 270 |
int Hue; /* Desired Hue */ |
| 271 |
int Saturation; /* Desired Satuation */ |
| 272 |
int RGBorCV; /* CV or RGB Input */ |
| 273 |
int VCRorCamera; /* VCR or Camera */ |
| 274 |
int ovrscnAvail, ovrscnOn; /* ovrscnAvail 1 if Overscan installed */ |
| 275 |
/* ovrscnOn 1 if overscan is stretching */ |
| 276 |
|
| 277 |
/* Display Registers */ |
| 278 |
int DisplayRegister[22]; |
| 279 |
}; |
| 280 |
|
| 281 |
struct M8Struct { |
| 282 |
int there; /* flag to indicate if m8 is present */ |
| 283 |
/* logical true if M8 present (i.e. 1) */ |
| 284 |
/* and logical false (0) otherwise */ |
| 285 |
int inOffset; /* input offset */ |
| 286 |
int inGain; /* input gain */ |
| 287 |
int inputMux; /* input channel */ |
| 288 |
int modeRegister; /* value of the mode register on the M8 top */ |
| 289 |
int inMap, outMap; /* active input/output color map */ |
| 290 |
int loopThru; /* logical flag if M8 loop-through is desired */ |
| 291 |
/* of CGA input 1---YES, 0---No */ |
| 292 |
int topFunction; /* currently selected top function */ |
| 293 |
int CGAInterlace; /* interlace mode for a CGA if used */ |
| 294 |
}; |
| 295 |
|
| 296 |
#define M8MODE 0x400 /* IO Offset for writes to M8 Mode register */ |
| 297 |
#define M8WRITE 0x402 /* Offset for writes to M8 function registers */ |
| 298 |
#define M8READ 0x802 /* Offset for reads from M8 function registers */ |
| 299 |
|
| 300 |
#define DEF_M8MODE 2 |
| 301 |
#define DEF_M8GAIN 50 |
| 302 |
#define DEF_M8OFFSET 50 |
| 303 |
#define DEF_M8MUX 0 |
| 304 |
#define DEF_M8INMAP 0 |
| 305 |
#define DEF_M8OUTMAP 0 |
| 306 |
#define DEF_CGAINTERLACE 3 |
| 307 |
|
| 308 |
|
| 309 |
struct hdStruct { |
| 310 |
char textSize; |
| 311 |
char mapType; |
| 312 |
char dataType; |
| 313 |
int mapOrig; |
| 314 |
int mapLength; |
| 315 |
char CMapBits; |
| 316 |
int XOffset; |
| 317 |
int YOffset; |
| 318 |
int x; |
| 319 |
int y; |
| 320 |
int dataBits, imType; |
| 321 |
} ; |
| 322 |
|
| 323 |
|
| 324 |
/* stroke font file */ |
| 325 |
|
| 326 |
typedef struct{ |
| 327 |
int width; /* width of character */ |
| 328 |
int height; /* height of char from baseline */ |
| 329 |
int descent; /* descent below baseline */ |
| 330 |
int index; /* index into stroke table */ |
| 331 |
} SFONTCHAR; |
| 332 |
|
| 333 |
typedef struct { |
| 334 |
int dx; /* dx of character */ |
| 335 |
int dy; /* dy of character */ |
| 336 |
int dd; /* dy of descenders */ |
| 337 |
int first; /* value of first char in font */ |
| 338 |
int last; /* value of last char in font */ |
| 339 |
int *strokes; /* where the strokes are located */ |
| 340 |
SFONTCHAR *info; /* info on each character */ |
| 341 |
} SFONT; |
| 342 |
|
| 343 |
|
| 344 |
#ifdef __cplusplus |
| 345 |
} |
| 346 |
#endif |
| 347 |
#endif /* _RAD_TARDEV_H_ */ |
| 348 |
|
