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/* RCSid: $Id$ */ |
| 2 |
/* |
| 3 |
* Board types used for targa->boardType |
| 4 |
*/ |
| 5 |
#define TYPE_8 8 |
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#define TYPE_16 16 |
| 7 |
#define TYPE_24 24 |
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#define TYPE_32 32 |
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#define TYPE_M8 -8 |
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|
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/* |
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* TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel |
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*/ |
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|
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#define XMIN 0 |
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#define YMIN 0 |
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#define XMAX 512 /* maximum X value */ |
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#define YMAX 512 /* maximum Y value */ |
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#define XRES 512 /* X resolution */ |
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#define YRES 512 /* Y Resolution */ |
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#define YVISMAX (2*targa->LinesPerField) /* Maximum visible Y coordinate */ |
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#define YVISMIN 0 /* Minimum visible Y coordiate */ |
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#define DEF_ROWS 400 /* Default number of rows */ |
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|
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|
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#define DEF_IOBASE 0x220 |
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#define IOBASE targa->iobase /* io base location of graphics registers */ |
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#define MEMSEG targa->memloc /* use the variable so we can use */ |
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#define SCNSEG targa->memloc /* the one defined in TARGA */ |
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#define SRCBANK (targa->memloc+0x0800) /* use high-bank as source bank */ |
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#define DESTBANK targa->memloc /* use lo-bank as destination bank */ |
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#define DEF_MEMSEG 0xa000 /* Default screen memory */ |
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|
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/* |
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* Output register definitions |
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*/ |
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#define MODEREG (IOBASE+0xC00) /* Mode Register address */ |
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#define MASKREG (IOBASE+0x800) /* Mask Registers */ |
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#define UNDERREG (IOBASE+0x800) /* Underscan register */ |
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#define OVERREG (IOBASE+0x802) /* overscan register */ |
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#define DESTREG (IOBASE+0x802) /* Address of Page Select Lower Register */ |
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#define SRCREG (IOBASE+0x803) /* Address of Page Select Upper Register */ |
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#define VCRCON (IOBASE+0x400) /* Address of Contrast/VidSrc Register */ |
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#define BLNDREG VCRCON |
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#define SATHUE (IOBASE+0x402) /* Satuation/Hue Register address */ |
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#define DRREG (IOBASE+0x401) /* ADDRESS OF Controller Write Register */ |
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#define VERTPAN (IOBASE+0x403) /* Address of Vertical Pan Register */ |
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#define BORDER (IOBASE) /* Address of Page Select Lower Register */ |
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|
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|
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/* |
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* Input register definitions |
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*/ |
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#define VIDEOSTATUS (IOBASE+0xC02) /* Video Status Register */ |
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#define RASTERREG (IOBASE+0xC00) /* Raster counter register */ |
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|
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|
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|
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/* |
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* Default register values |
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*/ |
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#define DEF_MODE 1 /* Default mode register value */ |
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/* Memory selected, 512x512, 1x */ |
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/* Display mode */ |
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#define DEF_MASK 0 /* default memory mask */ |
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#define DEF_SATURATION 0x4 /* default saturation value */ |
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#define DEF_HUE 0x10 /* default hue value */ |
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#define DEF_CONTRAST 0x10 /* default contrast value */ |
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#define DEF_VIDSRC 0 /* default video source value - Composite */ |
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#define DEF_VERTPAN 56 /* assumes 400-line output */ |
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#define DEF_BORDER 0 /* default border color */ |
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|
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|
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/* |
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* MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS |
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*/ |
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/* |
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* ****************************************************** |
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* MODE REGISTERS |
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* ****************************************************** |
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*/ |
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#define MSK_MSEL 0xfffC /* memory select bits */ |
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#define SHF_MSEL 0x0000 |
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#define MSEL 1 |
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|
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#define MSK_IBIT 0xfffb /* Interlace bit */ |
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#define SHF_IBIT 2 |
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|
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#define MSK_RES 0xFFC7 /* disp. resolution and screen select bits */ |
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#define SHF_RES 3 |
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#define S0_512X512_0 0 /* 512x512 resolution screen */ |
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#define S1_512X512_1 1 |
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#define S2_512X256_0 2 /* 512x256 resolution screen 0 */ |
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#define S3_512X256_1 3 /* 512x256 resolution screen 1 */ |
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#define S4_256X256_0 4 /* 256x256 resolution screen 0 */ |
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#define S5_256X256_1 5 /* .... */ |
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#define S6_256X256_2 6 |
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#define S7_256X256_3 7 |
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|
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#define MSK_REGWRITE 0xFFBF /* mask for display register write */ |
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#define SHF_REGWRITE 6 |
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#define REGINDEX 0 /* to write an index value */ |
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#define REGVALUE 1 /* to write a value */ |
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|
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#define MSK_BIT9 0xFF7F /* maks for high-order bit of DR's */ |
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#define SHF_BIT9 7 |
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|
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#define MSK_TAPBITS 0xFCFF /* mask for setting the tap bits */ |
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#define SHF_TAPBITS 8 |
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|
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#define MSK_ZOOM 0xF3FF /* Mask for zoom factor */ |
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#define SHF_ZOOM 10 |
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|
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#define MSK_DISPLAY 0xCFFF /* Mask for display mode */ |
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#define SHF_DISPLAY 12 |
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#define MEMORY_MODE 0 |
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#define LIVE_FIXED 1 |
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#define OVERLAY_MODE 2 |
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#define LIVE_LIVE 3 |
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#define DEF_DISPLAY 0 |
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|
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#define MSK_CAPTURE 0xBFFF /* Mask for capture bit */ |
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#define SHF_CAPTURE 14 |
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|
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#define MSK_GENLOCK 0x7FFF /* MASK FOR GENLOCK */ |
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#define SHF_GENLOCK 15 |
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#define DEF_GENLOCK 0 |
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/* |
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* Video status input register |
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*/ |
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#define FIELDBIT 0x0001 |
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#define VIDEOLOSS 0x0002 |
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/* |
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* VIDEO SOURCE/CONTROL REGISTER |
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*/ |
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#define MSK_CONTRAST 0xFFC1 |
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#define SHF_CONTRAST 1 |
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#define MAX_CONTRAST 0x1f |
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|
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#define MSK_RGBORCV 0xBF |
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#define SHF_RGBORCV 6 |
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#define RGB 1 |
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#define CV 0 |
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|
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#define MSK_VCRORCAMERA 0x7F |
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#define SHF_VCRORCAMERA 7 |
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#define VCR 1 |
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#define CAMERA 0 |
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|
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/* |
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* HUE/SATUATION REGISTER |
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*/ |
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#define MSK_HUE 0xE0 |
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#define SHF_HUE 0 |
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#define MAX_HUE 0x1f |
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|
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#define MSK_SATURATION 0x1F |
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#define SHF_SATURATION 5 |
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#define MAX_SATURATION 0x07 |
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|
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|
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/* |
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* ********************************************* |
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* Display register settings |
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* ********************************************* |
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* |
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* Screen Positioning Registers: |
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* DR 0-3 |
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*/ |
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#define LEFTBORDER 0 |
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#define DEF_LEFT 85 |
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#define MIN_LEFT 75 |
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#define MAX_LEFT 95 |
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#define RIGHTBORDER 1 |
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#define DEF_RIGHT (DEF_LEFT+256) |
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#define TOPBORDER 2 |
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#define DEF_TOP 40 |
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#define MIN_TOP 20 |
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#define BOTTOMBORDER 3 |
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#define DEF_BOTTOM (DEFTOP+DEFROWS/2) |
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#define MAX_BOTTOM 261 |
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|
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/* |
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* REgisters which track 0-3 |
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*/ |
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#define DR8 8 |
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#define PRESHIFT DR8 |
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#define EQU_DR8 DR0 |
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#define DR9 9 |
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#define EQU_DR9 DR1 |
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#define DR10 10 |
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#define EQU_DR10 DR2 |
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#define DR11 11 |
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#define EQU_DR11 DR3 |
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|
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/* |
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* REQUIRED REGISTERS |
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*/ |
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#define DR4 4 |
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#define DEF_DR4 352 |
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#define DR5 5 |
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#define DEF_DR5 1 |
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#define DR6 6 |
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#define DEF_DR6 0 |
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#define DR7 7 |
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#define DEF_DR7 511 |
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#define DR12 12 |
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#define DEF_DR12 20 |
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#define DR13 13 |
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#define DEF_DR13 22 |
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#define DR14 14 |
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#define DEF_DR14 0 |
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#define DR15 15 |
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#define DEF_DR15 511 |
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#define DR16 16 |
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#define DEF_DR16 0 |
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#define DR17 17 |
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#define DEF_DR17 0 |
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#define DR18 18 |
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#define DEF_DR18 0 |
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#define DR19 19 |
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#define DEF_DR19 4 |
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|
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/* interlace mode register & parameters */ |
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#define DR20 20 |
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#define INTREG 0x14 |
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#define DEF_INT 0 /* default to interlace mode 0 */ |
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#define MSK_INTERLACE 0x0003 |
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|
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|
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|
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struct TARStruct { |
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/* Board Configuration */ |
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int memloc; /* memory segment */ |
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int iobase; /* IOBASE segment */ |
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int BytesPerPixel; /* number of words per pixel */ |
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int RowsPerBank; /* number of row per 64K bank */ |
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int MaxBanks; /* maximum bank id */ |
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int AddressShift; /* number of bits to shift address */ |
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|
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/* Control registers */ |
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int mode; /* mode register */ |
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int Mask; /* mask register */ |
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int PageMode; /* current page mode (screen res. and page) */ |
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unsigned PageLower; /* Lower Page Select register */ |
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unsigned PageUpper; /* upper Page select register */ |
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int VCRCon; /* VCRContract register */ |
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int SatHue; /* Hue and Saturation register */ |
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long BorderColor; /* Border color register */ |
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int VertShift; /* Vertical Pan Register */ |
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|
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int PanXOrig, PanYOrig; /* x,y pan origin */ |
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|
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/* TARGA-SET PARAMETERS */ |
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int boardType; /* See TYPE_XX IN THIS FILE */ |
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/* FOR DEFINITION OF Board Types */ |
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int xOffset; /* X-offset */ |
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int yOffset; /* Y-Offset */ |
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int LinesPerField; /* maximum visible row count */ |
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int InterlaceMode; /* desired interlace mode */ |
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int AlwaysGenLock; /* Genlock always on or not */ |
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int Contrast; /* Desired Contrast */ |
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int Hue; /* Desired Hue */ |
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int Saturation; /* Desired Satuation */ |
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int RGBorCV; /* CV or RGB Input */ |
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int VCRorCamera; /* VCR or Camera */ |
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int ovrscnAvail, ovrscnOn; /* ovrscnAvail 1 if Overscan installed */ |
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/* ovrscnOn 1 if overscan is stretching */ |
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|
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/* Display Registers */ |
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int DisplayRegister[22]; |
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}; |
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|
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struct M8Struct { |
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int there; /* flag to indicate if m8 is present */ |
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/* logical true if M8 present (i.e. 1) */ |
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/* and logical false (0) otherwise */ |
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int inOffset; /* input offset */ |
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int inGain; /* input gain */ |
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int inputMux; /* input channel */ |
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int modeRegister; /* value of the mode register on the M8 top */ |
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int inMap, outMap; /* active input/output color map */ |
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int loopThru; /* logical flag if M8 loop-through is desired */ |
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/* of CGA input 1---YES, 0---No */ |
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int topFunction; /* currently selected top function */ |
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int CGAInterlace; /* interlace mode for a CGA if used */ |
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}; |
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|
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#define M8MODE 0x400 /* IO Offset for writes to M8 Mode register */ |
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#define M8WRITE 0x402 /* Offset for writes to M8 function registers */ |
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#define M8READ 0x802 /* Offset for reads from M8 function registers */ |
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|
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#define DEF_M8MODE 2 |
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#define DEF_M8GAIN 50 |
| 295 |
#define DEF_M8OFFSET 50 |
| 296 |
#define DEF_M8MUX 0 |
| 297 |
#define DEF_M8INMAP 0 |
| 298 |
#define DEF_M8OUTMAP 0 |
| 299 |
#define DEF_CGAINTERLACE 3 |
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|
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|
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struct hdStruct { |
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char textSize; |
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char mapType; |
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char dataType; |
| 306 |
int mapOrig; |
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int mapLength; |
| 308 |
char CMapBits; |
| 309 |
int XOffset; |
| 310 |
int YOffset; |
| 311 |
int x; |
| 312 |
int y; |
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int dataBits, imType; |
| 314 |
} ; |
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|
| 316 |
|
| 317 |
/* stroke font file */ |
| 318 |
|
| 319 |
typedef struct{ |
| 320 |
int width; /* width of character */ |
| 321 |
int height; /* height of char from baseline */ |
| 322 |
int descent; /* descent below baseline */ |
| 323 |
int index; /* index into stroke table */ |
| 324 |
} SFONTCHAR; |
| 325 |
|
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typedef struct { |
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int dx; /* dx of character */ |
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int dy; /* dy of character */ |
| 329 |
int dd; /* dy of descenders */ |
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int first; /* value of first char in font */ |
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int last; /* value of last char in font */ |
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int *strokes; /* where the strokes are located */ |
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SFONTCHAR *info; /* info on each character */ |
| 334 |
} SFONT; |
