| 1 |
greg |
1.2 |
/* Copyright 1988 Regents of the University of California */
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| 2 |
greg |
1.1 |
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| 3 |
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/* SCCSid "$SunId$ LBL" */
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| 4 |
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| 5 |
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/*
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| 6 |
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* Board types used for targa->boardType
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| 7 |
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*/
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| 8 |
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#define TYPE_8 8
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| 9 |
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#define TYPE_16 16
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| 10 |
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#define TYPE_24 24
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| 11 |
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#define TYPE_32 32
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| 12 |
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#define TYPE_M8 -8
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| 14 |
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/*
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| 15 |
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* TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel
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*/
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| 18 |
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#define XMIN 0
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| 19 |
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#define YMIN 0
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| 20 |
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#define XMAX 512 /* maximum X value */
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| 21 |
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#define YMAX 512 /* maximum Y value */
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| 22 |
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#define XRES 512 /* X resolution */
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| 23 |
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#define YRES 512 /* Y Resolution */
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#define YVISMAX (2*targa->LinesPerField) /* Maximum visible Y coordinate */
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#define YVISMIN 0 /* Minimum visible Y coordiate */
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#define DEF_ROWS 400 /* Default number of rows */
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| 28 |
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| 29 |
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#define DEF_IOBASE 0x220
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| 30 |
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#define IOBASE targa->iobase /* io base location of graphics registers */
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#define MEMSEG targa->memloc /* use the variable so we can use */
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#define SCNSEG targa->memloc /* the one defined in TARGA */
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#define SRCBANK (targa->memloc+0x0800) /* use high-bank as source bank */
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#define DESTBANK targa->memloc /* use lo-bank as destination bank */
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#define DEF_MEMSEG 0xa000 /* Default screen memory */
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| 37 |
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/*
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* Output register definitions
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| 39 |
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*/
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#define MODEREG (IOBASE+0xC00) /* Mode Register address */
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#define MASKREG (IOBASE+0x800) /* Mask Registers */
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#define UNDERREG (IOBASE+0x800) /* Underscan register */
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#define OVERREG (IOBASE+0x802) /* overscan register */
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#define DESTREG (IOBASE+0x802) /* Address of Page Select Lower Register */
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#define SRCREG (IOBASE+0x803) /* Address of Page Select Upper Register */
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#define VCRCON (IOBASE+0x400) /* Address of Contrast/VidSrc Register */
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#define BLNDREG VCRCON
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#define SATHUE (IOBASE+0x402) /* Satuation/Hue Register address */
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#define DRREG (IOBASE+0x401) /* ADDRESS OF Controller Write Register */
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#define VERTPAN (IOBASE+0x403) /* Address of Vertical Pan Register */
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#define BORDER (IOBASE) /* Address of Page Select Lower Register */
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| 53 |
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| 54 |
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/*
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* Input register definitions
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*/
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#define VIDEOSTATUS (IOBASE+0xC02) /* Video Status Register */
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#define RASTERREG (IOBASE+0xC00) /* Raster counter register */
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| 60 |
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| 61 |
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| 62 |
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/*
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* Default register values
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*/
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#define DEF_MODE 1 /* Default mode register value */
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/* Memory selected, 512x512, 1x */
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/* Display mode */
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#define DEF_MASK 0 /* default memory mask */
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#define DEF_SATURATION 0x4 /* default saturation value */
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#define DEF_HUE 0x10 /* default hue value */
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#define DEF_CONTRAST 0x10 /* default contrast value */
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#define DEF_VIDSRC 0 /* default video source value - Composite */
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#define DEF_VERTPAN 56 /* assumes 400-line output */
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#define DEF_BORDER 0 /* default border color */
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| 76 |
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| 77 |
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/*
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* MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS
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*/
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/*
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| 81 |
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* ******************************************************
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* MODE REGISTERS
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| 83 |
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* ******************************************************
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*/
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| 85 |
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#define MSK_MSEL 0xfffC /* memory select bits */
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| 86 |
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#define SHF_MSEL 0x0000
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#define MSEL 1
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| 88 |
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| 89 |
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#define MSK_IBIT 0xfffb /* Interlace bit */
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| 90 |
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#define SHF_IBIT 2
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| 91 |
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| 92 |
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#define MSK_RES 0xFFC7 /* disp. resolution and screen select bits */
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#define SHF_RES 3
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#define S0_512X512_0 0 /* 512x512 resolution screen */
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#define S1_512X512_1 1
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| 96 |
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#define S2_512X256_0 2 /* 512x256 resolution screen 0 */
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| 97 |
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#define S3_512X256_1 3 /* 512x256 resolution screen 1 */
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| 98 |
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#define S4_256X256_0 4 /* 256x256 resolution screen 0 */
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| 99 |
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#define S5_256X256_1 5 /* .... */
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| 100 |
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#define S6_256X256_2 6
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| 101 |
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#define S7_256X256_3 7
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| 102 |
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| 103 |
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#define MSK_REGWRITE 0xFFBF /* mask for display register write */
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| 104 |
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#define SHF_REGWRITE 6
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#define REGINDEX 0 /* to write an index value */
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| 106 |
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#define REGVALUE 1 /* to write a value */
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| 107 |
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| 108 |
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#define MSK_BIT9 0xFF7F /* maks for high-order bit of DR's */
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| 109 |
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#define SHF_BIT9 7
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| 110 |
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| 111 |
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#define MSK_TAPBITS 0xFCFF /* mask for setting the tap bits */
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| 112 |
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#define SHF_TAPBITS 8
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| 113 |
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| 114 |
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#define MSK_ZOOM 0xF3FF /* Mask for zoom factor */
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#define SHF_ZOOM 10
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| 116 |
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| 117 |
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#define MSK_DISPLAY 0xCFFF /* Mask for display mode */
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| 118 |
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#define SHF_DISPLAY 12
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| 119 |
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#define MEMORY_MODE 0
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| 120 |
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#define LIVE_FIXED 1
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| 121 |
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#define OVERLAY_MODE 2
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| 122 |
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#define LIVE_LIVE 3
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| 123 |
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#define DEF_DISPLAY 0
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| 124 |
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| 125 |
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#define MSK_CAPTURE 0xBFFF /* Mask for capture bit */
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| 126 |
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#define SHF_CAPTURE 14
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| 127 |
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| 128 |
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#define MSK_GENLOCK 0x7FFF /* MASK FOR GENLOCK */
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| 129 |
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#define SHF_GENLOCK 15
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| 130 |
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#define DEF_GENLOCK 0
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| 131 |
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/*
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| 132 |
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* Video status input register
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| 133 |
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*/
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| 134 |
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#define FIELDBIT 0x0001
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| 135 |
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#define VIDEOLOSS 0x0002
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| 136 |
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/*
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| 137 |
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* VIDEO SOURCE/CONTROL REGISTER
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| 138 |
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*/
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| 139 |
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#define MSK_CONTRAST 0xFFC1
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| 140 |
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#define SHF_CONTRAST 1
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| 141 |
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#define MAX_CONTRAST 0x1f
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| 142 |
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| 143 |
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#define MSK_RGBORCV 0xBF
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| 144 |
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#define SHF_RGBORCV 6
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| 145 |
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#define RGB 1
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| 146 |
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#define CV 0
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| 147 |
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| 148 |
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#define MSK_VCRORCAMERA 0x7F
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| 149 |
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#define SHF_VCRORCAMERA 7
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| 150 |
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#define VCR 1
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| 151 |
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#define CAMERA 0
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| 152 |
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| 153 |
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/*
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| 154 |
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* HUE/SATUATION REGISTER
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| 155 |
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*/
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| 156 |
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#define MSK_HUE 0xE0
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| 157 |
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#define SHF_HUE 0
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| 158 |
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#define MAX_HUE 0x1f
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| 159 |
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| 160 |
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#define MSK_SATURATION 0x1F
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| 161 |
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#define SHF_SATURATION 5
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#define MAX_SATURATION 0x07
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| 163 |
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| 164 |
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| 165 |
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/*
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| 166 |
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* *********************************************
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| 167 |
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* Display register settings
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| 168 |
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* *********************************************
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| 169 |
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*
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| 170 |
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* Screen Positioning Registers:
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| 171 |
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* DR 0-3
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| 172 |
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*/
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| 173 |
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#define LEFTBORDER 0
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| 174 |
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#define DEF_LEFT 85
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| 175 |
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#define MIN_LEFT 75
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| 176 |
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#define MAX_LEFT 95
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| 177 |
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#define RIGHTBORDER 1
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| 178 |
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#define DEF_RIGHT (DEF_LEFT+256)
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| 179 |
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#define TOPBORDER 2
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| 180 |
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#define DEF_TOP 40
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| 181 |
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#define MIN_TOP 20
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| 182 |
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#define BOTTOMBORDER 3
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| 183 |
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#define DEF_BOTTOM (DEFTOP+DEFROWS/2)
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#define MAX_BOTTOM 261
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| 185 |
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| 186 |
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/*
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| 187 |
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* REgisters which track 0-3
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| 188 |
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*/
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| 189 |
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#define DR8 8
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| 190 |
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#define PRESHIFT DR8
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#define EQU_DR8 DR0
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| 192 |
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#define DR9 9
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#define EQU_DR9 DR1
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| 194 |
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#define DR10 10
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#define EQU_DR10 DR2
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#define DR11 11
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#define EQU_DR11 DR3
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| 198 |
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| 199 |
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/*
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| 200 |
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* REQUIRED REGISTERS
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| 201 |
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*/
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| 202 |
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#define DR4 4
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| 203 |
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#define DEF_DR4 352
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| 204 |
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#define DR5 5
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| 205 |
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#define DEF_DR5 1
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| 206 |
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#define DR6 6
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| 207 |
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#define DEF_DR6 0
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| 208 |
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#define DR7 7
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| 209 |
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#define DEF_DR7 511
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| 210 |
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#define DR12 12
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| 211 |
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#define DEF_DR12 20
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| 212 |
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#define DR13 13
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| 213 |
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#define DEF_DR13 22
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| 214 |
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#define DR14 14
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| 215 |
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#define DEF_DR14 0
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| 216 |
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#define DR15 15
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| 217 |
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#define DEF_DR15 511
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| 218 |
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#define DR16 16
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| 219 |
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#define DEF_DR16 0
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| 220 |
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#define DR17 17
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| 221 |
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#define DEF_DR17 0
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| 222 |
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#define DR18 18
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| 223 |
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#define DEF_DR18 0
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| 224 |
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#define DR19 19
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| 225 |
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#define DEF_DR19 4
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| 226 |
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| 227 |
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/* interlace mode register & parameters */
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| 228 |
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#define DR20 20
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| 229 |
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#define INTREG 0x14
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| 230 |
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#define DEF_INT 0 /* default to interlace mode 0 */
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| 231 |
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#define MSK_INTERLACE 0x0003
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| 232 |
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| 233 |
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| 234 |
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| 235 |
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struct TARStruct {
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| 236 |
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/* Board Configuration */
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| 237 |
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int memloc; /* memory segment */
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| 238 |
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int iobase; /* IOBASE segment */
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| 239 |
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int BytesPerPixel; /* number of words per pixel */
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| 240 |
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int RowsPerBank; /* number of row per 64K bank */
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| 241 |
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int MaxBanks; /* maximum bank id */
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| 242 |
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int AddressShift; /* number of bits to shift address */
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| 243 |
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| 244 |
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/* Control registers */
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| 245 |
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int mode; /* mode register */
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| 246 |
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int Mask; /* mask register */
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| 247 |
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int PageMode; /* current page mode (screen res. and page) */
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| 248 |
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unsigned PageLower; /* Lower Page Select register */
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| 249 |
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unsigned PageUpper; /* upper Page select register */
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| 250 |
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int VCRCon; /* VCRContract register */
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| 251 |
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int SatHue; /* Hue and Saturation register */
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| 252 |
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long BorderColor; /* Border color register */
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| 253 |
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int VertShift; /* Vertical Pan Register */
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| 254 |
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| 255 |
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int PanXOrig, PanYOrig; /* x,y pan origin */
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| 256 |
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| 257 |
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/* TARGA-SET PARAMETERS */
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| 258 |
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int boardType; /* See TYPE_XX IN THIS FILE */
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| 259 |
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/* FOR DEFINITION OF Board Types */
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| 260 |
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int xOffset; /* X-offset */
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| 261 |
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int yOffset; /* Y-Offset */
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| 262 |
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int LinesPerField; /* maximum visible row count */
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| 263 |
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int InterlaceMode; /* desired interlace mode */
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| 264 |
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int AlwaysGenLock; /* Genlock always on or not */
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| 265 |
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int Contrast; /* Desired Contrast */
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| 266 |
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int Hue; /* Desired Hue */
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| 267 |
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int Saturation; /* Desired Satuation */
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| 268 |
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int RGBorCV; /* CV or RGB Input */
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| 269 |
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int VCRorCamera; /* VCR or Camera */
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| 270 |
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int ovrscnAvail, ovrscnOn; /* ovrscnAvail 1 if Overscan installed */
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| 271 |
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/* ovrscnOn 1 if overscan is stretching */
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| 272 |
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| 273 |
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/* Display Registers */
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| 274 |
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int DisplayRegister[22];
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| 275 |
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};
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| 276 |
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| 277 |
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struct M8Struct {
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| 278 |
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int there; /* flag to indicate if m8 is present */
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| 279 |
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/* logical true if M8 present (i.e. 1) */
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| 280 |
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/* and logical false (0) otherwise */
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| 281 |
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int inOffset; /* input offset */
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| 282 |
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int inGain; /* input gain */
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| 283 |
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int inputMux; /* input channel */
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| 284 |
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int modeRegister; /* value of the mode register on the M8 top */
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| 285 |
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int inMap, outMap; /* active input/output color map */
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| 286 |
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int loopThru; /* logical flag if M8 loop-through is desired */
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| 287 |
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/* of CGA input 1---YES, 0---No */
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| 288 |
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int topFunction; /* currently selected top function */
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| 289 |
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int CGAInterlace; /* interlace mode for a CGA if used */
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| 290 |
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};
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| 291 |
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| 292 |
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#define M8MODE 0x400 /* IO Offset for writes to M8 Mode register */
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| 293 |
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#define M8WRITE 0x402 /* Offset for writes to M8 function registers */
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| 294 |
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#define M8READ 0x802 /* Offset for reads from M8 function registers */
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| 295 |
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| 296 |
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#define DEF_M8MODE 2
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| 297 |
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#define DEF_M8GAIN 50
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| 298 |
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#define DEF_M8OFFSET 50
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| 299 |
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#define DEF_M8MUX 0
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| 300 |
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#define DEF_M8INMAP 0
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| 301 |
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#define DEF_M8OUTMAP 0
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| 302 |
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#define DEF_CGAINTERLACE 3
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| 303 |
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| 304 |
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| 305 |
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struct hdStruct {
|
| 306 |
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char textSize;
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| 307 |
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char mapType;
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| 308 |
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char dataType;
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| 309 |
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int mapOrig;
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| 310 |
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int mapLength;
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| 311 |
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char CMapBits;
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| 312 |
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int XOffset;
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| 313 |
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int YOffset;
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| 314 |
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int x;
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| 315 |
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int y;
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| 316 |
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int dataBits, imType;
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| 317 |
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} ;
|
| 318 |
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| 319 |
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| 320 |
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/* stroke font file */
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| 321 |
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| 322 |
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typedef struct{
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| 323 |
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int width; /* width of character */
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| 324 |
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int height; /* height of char from baseline */
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| 325 |
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int descent; /* descent below baseline */
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| 326 |
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int index; /* index into stroke table */
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| 327 |
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} SFONTCHAR;
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| 328 |
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| 329 |
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typedef struct {
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| 330 |
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int dx; /* dx of character */
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| 331 |
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int dy; /* dy of character */
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| 332 |
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int dd; /* dy of descenders */
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| 333 |
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int first; /* value of first char in font */
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| 334 |
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int last; /* value of last char in font */
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| 335 |
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int *strokes; /* where the strokes are located */
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| 336 |
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SFONTCHAR *info; /* info on each character */
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| 337 |
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} SFONT;
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