src/px/tardev.h

/* Copyright 1988 Regents of the University of California */

/* SCCSid "$SunId$ LBL" */

/*
 *              Board types used for targa->boardType
 */
#define    TYPE_8        8
#define    TYPE_16  16
#define    TYPE_24  24
#define    TYPE_32  32
#define    TYPE_M8  -8

/*
 * TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel      
 */

#define XMIN    0
#define YMIN    0
#define XMAX    512                     /*  maximum X value */
#define YMAX    512                     /*  maximum Y value */
#define XRES    512                     /*  X resolution */
#define YRES    512                     /*  Y Resolution */
#define YVISMAX (2*targa->LinesPerField)        /*   Maximum visible Y coordinate */
#define YVISMIN 0                           /*   Minimum visible Y coordiate */
#define DEF_ROWS 400                    /*  Default number of rows */


#define DEF_IOBASE   0x220
#define IOBASE  targa->iobase   /* io base location of graphics registers */
#define MEMSEG   targa->memloc   /*  use the variable so we can use */
#define SCNSEG   targa->memloc   /*  the one defined in TARGA */
#define SRCBANK  (targa->memloc+0x0800)   /*  use high-bank as source bank */
#define DESTBANK targa->memloc                    /*  use lo-bank as destination bank */
#define DEF_MEMSEG 0xa000               /* Default screen memory */

/*
 *                              Output register definitions
 */
#define MODEREG (IOBASE+0xC00)  /*  Mode Register address */
#define MASKREG (IOBASE+0x800)  /*  Mask Registers */
#define UNDERREG        (IOBASE+0x800)  /*  Underscan register */
#define OVERREG         (IOBASE+0x802)  /*  overscan register */
#define DESTREG (IOBASE+0x802)  /*  Address of Page Select Lower Register */
#define SRCREG  (IOBASE+0x803)  /*  Address of Page Select Upper Register */
#define VCRCON  (IOBASE+0x400)  /*  Address of Contrast/VidSrc Register */
#define BLNDREG  VCRCON
#define SATHUE  (IOBASE+0x402)  /* Satuation/Hue Register address */
#define DRREG (IOBASE+0x401)    /* ADDRESS OF Controller Write Register */
#define VERTPAN (IOBASE+0x403)  /*  Address of Vertical Pan Register */
#define BORDER  (IOBASE)        /*  Address of Page Select Lower Register */


/*
 *                              Input register definitions
 */
#define VIDEOSTATUS     (IOBASE+0xC02)  /*  Video Status Register */
#define RASTERREG       (IOBASE+0xC00)          /* Raster counter register */


/*
 *                      Default register values 
 */
#define DEF_MODE 1                              /*  Default mode register value */
                                                                /*   Memory selected, 512x512, 1x */
                                                                /*   Display mode */
#define DEF_MASK 0                              /*  default memory mask */
#define DEF_SATURATION  0x4                     /* default saturation value */
#define DEF_HUE 0x10            /* default hue value */
#define DEF_CONTRAST    0x10            /* default contrast value */
#define DEF_VIDSRC  0       /* default video source value - Composite */
#define DEF_VERTPAN 56          /*  assumes 400-line output */
#define DEF_BORDER  0           /*  default border color */


/*  
 *                      MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS
 */
/*
 *   ******************************************************
 *                                      MODE REGISTERS
 *   ******************************************************
 */
#define MSK_MSEL 0xfffC         /*  memory select bits */
#define SHF_MSEL 0x0000
#define MSEL     1

#define MSK_IBIT 0xfffb         /*  Interlace bit */
#define SHF_IBIT 2

#define MSK_RES  0xFFC7                 /*   disp. resolution and screen select bits */
#define SHF_RES  3
#define S0_512X512_0            0               /*   512x512 resolution screen */
#define S1_512X512_1            1
#define S2_512X256_0            2               /*   512x256 resolution screen 0 */
#define S3_512X256_1            3               /*   512x256 resolution screen 1 */
#define S4_256X256_0            4               /*   256x256 resolution screen 0 */
#define S5_256X256_1            5               /*      ....   */
#define S6_256X256_2            6
#define S7_256X256_3            7

#define MSK_REGWRITE    0xFFBF  /*   mask for display register write */
#define SHF_REGWRITE    6
#define REGINDEX                0               /*  to write an index value */
#define REGVALUE                1               /*  to write a value */

#define MSK_BIT9                0xFF7F  /*  maks for high-order bit of DR's */
#define SHF_BIT9                7               

#define MSK_TAPBITS             0xFCFF  /*  mask for setting the tap bits */
#define SHF_TAPBITS             8       

#define MSK_ZOOM                0xF3FF  /*  Mask for zoom factor */
#define SHF_ZOOM                10

#define MSK_DISPLAY             0xCFFF  /*  Mask for display mode */
#define SHF_DISPLAY             12
#define MEMORY_MODE             0
#define LIVE_FIXED              1
#define OVERLAY_MODE    2
#define LIVE_LIVE               3
#define DEF_DISPLAY             0

#define MSK_CAPTURE             0xBFFF  /*  Mask for capture bit */
#define SHF_CAPTURE     14

#define MSK_GENLOCK             0x7FFF  /*  MASK FOR GENLOCK */
#define SHF_GENLOCK             15
#define DEF_GENLOCK             0
/*
 *              Video status input register
 */
#define FIELDBIT        0x0001
#define VIDEOLOSS 0x0002
/*
 *      VIDEO SOURCE/CONTROL REGISTER
 */
#define MSK_CONTRAST    0xFFC1
#define SHF_CONTRAST    1
#define MAX_CONTRAST    0x1f

#define MSK_RGBORCV    0xBF
#define SHF_RGBORCV     6
#define RGB                     1
#define CV                              0

#define MSK_VCRORCAMERA 0x7F
#define SHF_VCRORCAMERA    7
#define VCR                             1
#define CAMERA                          0

 /* 
  *       HUE/SATUATION REGISTER
  */
#define MSK_HUE                 0xE0
#define SHF_HUE                 0
#define MAX_HUE         0x1f

#define MSK_SATURATION  0x1F
#define SHF_SATURATION  5
#define MAX_SATURATION  0x07


/*
 *  *********************************************
 *                      Display register settings
 *  *********************************************
 *
 *      Screen Positioning Registers:
 *              DR 0-3
 */
#define  LEFTBORDER     0
#define  DEF_LEFT   85
#define  MIN_LEFT       75
#define  MAX_LEFT       95
#define  RIGHTBORDER    1
#define  DEF_RIGHT       (DEF_LEFT+256)
#define  TOPBORDER      2
#define  DEF_TOP                40
#define  MIN_TOP        20
#define  BOTTOMBORDER   3
#define  DEF_BOTTOM     (DEFTOP+DEFROWS/2)
#define  MAX_BOTTOM     261

/*
 *      REgisters which track 0-3
 */
#define DR8     8
#define PRESHIFT        DR8
#define EQU_DR8 DR0
#define DR9     9
#define EQU_DR9 DR1
#define DR10    10
#define EQU_DR10        DR2
#define DR11    11
#define EQU_DR11        DR3

/*
 *      REQUIRED REGISTERS
 */
#define DR4     4
#define DEF_DR4 352
#define DR5     5
#define DEF_DR5 1
#define DR6     6
#define DEF_DR6 0
#define DR7     7
#define DEF_DR7 511
#define DR12    12
#define DEF_DR12        20
#define DR13    13
#define DEF_DR13        22
#define DR14    14
#define DEF_DR14        0
#define DR15    15
#define DEF_DR15        511
#define DR16    16
#define DEF_DR16        0
#define DR17    17
#define DEF_DR17        0
#define DR18    18
#define DEF_DR18        0
#define DR19    19
#define DEF_DR19        4

/* interlace mode register & parameters */
#define DR20    20
#define INTREG  0x14
#define DEF_INT  0              /*  default to interlace mode 0 */
#define MSK_INTERLACE 0x0003


struct  TARStruct {
        /*                      Board Configuration */
        int   memloc;   /* memory segment */
        int   iobase;   /*  IOBASE segment */
        int   BytesPerPixel;  /* number of words per pixel */
        int   RowsPerBank;   /* number of row per 64K bank */
        int       MaxBanks;             /*   maximum bank id */
        int   AddressShift; /*   number of bits to shift address */

        /*                      Control registers */
        int  mode;              /*  mode register */
        int  Mask;              /*  mask register */
        int  PageMode;  /*  current page mode (screen res. and page) */
        unsigned  PageLower;            /*  Lower Page Select register */
        unsigned  PageUpper;            /*  upper Page select register */
        int  VCRCon;            /*  VCRContract register */
        int  SatHue;            /* Hue and Saturation register */
        long  BorderColor;      /*  Border color register */
        int  VertShift; /*  Vertical Pan Register */

        int     PanXOrig, PanYOrig;     /* x,y pan origin */

        /*                       TARGA-SET PARAMETERS */ 
        int  boardType;         /*  See TYPE_XX  IN THIS FILE */
                                                /*  FOR DEFINITION OF Board Types */
        int  xOffset;           /* X-offset */
        int  yOffset;           /*  Y-Offset */
        int  LinesPerField;     /*  maximum visible row count */
        int  InterlaceMode;     /*  desired interlace mode */
        int  AlwaysGenLock;             /*  Genlock always on or not  */
        int  Contrast;          /*  Desired Contrast */
        int  Hue;               /*  Desired Hue */
        int  Saturation;        /*  Desired Satuation */
        int  RGBorCV;           /*  CV or RGB Input */
        int  VCRorCamera;       /*  VCR or Camera */
        int  ovrscnAvail, ovrscnOn; /*  ovrscnAvail   1  if Overscan installed */
                                                                /*  ovrscnOn  1 if overscan is stretching */
        
        /*                      Display Registers */
        int     DisplayRegister[22];
        };

struct  M8Struct {
        int  there;      /*  flag to indicate if m8 is present */
                                         /*  logical true if M8 present (i.e. 1) */
                                         /*  and logical false (0) otherwise */
        int  inOffset;   /*  input offset */
        int  inGain;     /*  input gain */
        int  inputMux;  /*  input channel */
        int  modeRegister;    /*   value of the mode register on the M8 top */
        int  inMap, outMap;  /*  active input/output color map */
        int  loopThru;          /*   logical flag if M8 loop-through is desired */
                                                /*  of CGA input 1---YES,  0---No     */
    int  topFunction;   /*  currently selected top function */
        int  CGAInterlace;  /*  interlace mode for  a CGA if used */
};

#define M8MODE  0x400    /*  IO Offset for writes to M8 Mode register */
#define M8WRITE 0x402    /*  Offset for writes to M8 function registers */
#define M8READ  0x802    /*  Offset for reads from M8 function registers */

#define DEF_M8MODE              2
#define DEF_M8GAIN              50
#define DEF_M8OFFSET    50
#define DEF_M8MUX               0
#define DEF_M8INMAP             0
#define DEF_M8OUTMAP    0
#define DEF_CGAINTERLACE        3


struct hdStruct {
        char textSize;
        char mapType;
        char dataType;
        int  mapOrig;
        int  mapLength;
        char CMapBits;
        int  XOffset;
        int  YOffset;
        int  x;
        int  y;
        int  dataBits, imType;
        } ;


/* stroke font file */

typedef struct{
        int width;                      /* width of character */
        int height;                     /* height of char from baseline */
        int descent;                    /* descent below baseline */
        int index;                      /* index into stroke table */
} SFONTCHAR;

typedef struct {
        int dx;                         /* dx of character */
        int dy;                         /* dy of character */
        int dd;                         /* dy of descenders */
        int first;                      /* value of first char in font */
        int last;                       /* value of last char in font */
        int *strokes;                   /* where the strokes are located */
        SFONTCHAR *info;                /* info on each character */
} SFONT;
Revision:	1.2
Committed:	Thu Feb 2 14:10:29 1989 UTC (35 years, 3 months ago) by greg
Content type:	text/plain
Branch:	MAIN
Changes since 1.1:	+1 -3 lines
Log Message:	Fixed SCCSid
#	User	Rev	Content
1	greg	1.2	/* Copyright 1988 Regents of the University of California */
2	greg	1.1
3			/* SCCSid "$SunId$ LBL" */
4
5			/*
6			* Board types used for targa->boardType
7			*/
8			#define TYPE_8 8
9			#define TYPE_16 16
10			#define TYPE_24 24
11			#define TYPE_32 32
12			#define TYPE_M8 -8
13
14			/*
15			* TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel
16			*/
17
18			#define XMIN 0
19			#define YMIN 0
20			#define XMAX 512 /* maximum X value */
21			#define YMAX 512 /* maximum Y value */
22			#define XRES 512 /* X resolution */
23			#define YRES 512 /* Y Resolution */
24			#define YVISMAX (2targa->LinesPerField) / Maximum visible Y coordinate */
25			#define YVISMIN 0 /* Minimum visible Y coordiate */
26			#define DEF_ROWS 400 /* Default number of rows */
27
28
29			#define DEF_IOBASE 0x220
30			#define IOBASE targa->iobase /* io base location of graphics registers */
31			#define MEMSEG targa->memloc /* use the variable so we can use */
32			#define SCNSEG targa->memloc /* the one defined in TARGA */
33			#define SRCBANK (targa->memloc+0x0800) /* use high-bank as source bank */
34			#define DESTBANK targa->memloc /* use lo-bank as destination bank */
35			#define DEF_MEMSEG 0xa000 /* Default screen memory */
36
37			/*
38			* Output register definitions
39			*/
40			#define MODEREG (IOBASE+0xC00) /* Mode Register address */
41			#define MASKREG (IOBASE+0x800) /* Mask Registers */
42			#define UNDERREG (IOBASE+0x800) /* Underscan register */
43			#define OVERREG (IOBASE+0x802) /* overscan register */
44			#define DESTREG (IOBASE+0x802) /* Address of Page Select Lower Register */
45			#define SRCREG (IOBASE+0x803) /* Address of Page Select Upper Register */
46			#define VCRCON (IOBASE+0x400) /* Address of Contrast/VidSrc Register */
47			#define BLNDREG VCRCON
48			#define SATHUE (IOBASE+0x402) /* Satuation/Hue Register address */
49			#define DRREG (IOBASE+0x401) /* ADDRESS OF Controller Write Register */
50			#define VERTPAN (IOBASE+0x403) /* Address of Vertical Pan Register */
51			#define BORDER (IOBASE) /* Address of Page Select Lower Register */
52
53
54			/*
55			* Input register definitions
56			*/
57			#define VIDEOSTATUS (IOBASE+0xC02) /* Video Status Register */
58			#define RASTERREG (IOBASE+0xC00) /* Raster counter register */
59
60
61
62			/*
63			* Default register values
64			*/
65			#define DEF_MODE 1 /* Default mode register value */
66			/* Memory selected, 512x512, 1x */
67			/* Display mode */
68			#define DEF_MASK 0 /* default memory mask */
69			#define DEF_SATURATION 0x4 /* default saturation value */
70			#define DEF_HUE 0x10 /* default hue value */
71			#define DEF_CONTRAST 0x10 /* default contrast value */
72			#define DEF_VIDSRC 0 /* default video source value - Composite */
73			#define DEF_VERTPAN 56 /* assumes 400-line output */
74			#define DEF_BORDER 0 /* default border color */
75
76
77			/*
78			* MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS
79			*/
80			/*
81			* ******************************************************
82			* MODE REGISTERS
83			* ******************************************************
84			*/
85			#define MSK_MSEL 0xfffC /* memory select bits */
86			#define SHF_MSEL 0x0000
87			#define MSEL 1
88
89			#define MSK_IBIT 0xfffb /* Interlace bit */
90			#define SHF_IBIT 2
91
92			#define MSK_RES 0xFFC7 /* disp. resolution and screen select bits */
93			#define SHF_RES 3
94			#define S0_512X512_0 0 /* 512x512 resolution screen */
95			#define S1_512X512_1 1
96			#define S2_512X256_0 2 /* 512x256 resolution screen 0 */
97			#define S3_512X256_1 3 /* 512x256 resolution screen 1 */
98			#define S4_256X256_0 4 /* 256x256 resolution screen 0 */
99			#define S5_256X256_1 5 /* .... */
100			#define S6_256X256_2 6
101			#define S7_256X256_3 7
102
103			#define MSK_REGWRITE 0xFFBF /* mask for display register write */
104			#define SHF_REGWRITE 6
105			#define REGINDEX 0 /* to write an index value */
106			#define REGVALUE 1 /* to write a value */
107
108			#define MSK_BIT9 0xFF7F /* maks for high-order bit of DR's */
109			#define SHF_BIT9 7
110
111			#define MSK_TAPBITS 0xFCFF /* mask for setting the tap bits */
112			#define SHF_TAPBITS 8
113
114			#define MSK_ZOOM 0xF3FF /* Mask for zoom factor */
115			#define SHF_ZOOM 10
116
117			#define MSK_DISPLAY 0xCFFF /* Mask for display mode */
118			#define SHF_DISPLAY 12
119			#define MEMORY_MODE 0
120			#define LIVE_FIXED 1
121			#define OVERLAY_MODE 2
122			#define LIVE_LIVE 3
123			#define DEF_DISPLAY 0
124
125			#define MSK_CAPTURE 0xBFFF /* Mask for capture bit */
126			#define SHF_CAPTURE 14
127
128			#define MSK_GENLOCK 0x7FFF /* MASK FOR GENLOCK */
129			#define SHF_GENLOCK 15
130			#define DEF_GENLOCK 0
131			/*
132			* Video status input register
133			*/
134			#define FIELDBIT 0x0001
135			#define VIDEOLOSS 0x0002
136			/*
137			* VIDEO SOURCE/CONTROL REGISTER
138			*/
139			#define MSK_CONTRAST 0xFFC1
140			#define SHF_CONTRAST 1
141			#define MAX_CONTRAST 0x1f
142
143			#define MSK_RGBORCV 0xBF
144			#define SHF_RGBORCV 6
145			#define RGB 1
146			#define CV 0
147
148			#define MSK_VCRORCAMERA 0x7F
149			#define SHF_VCRORCAMERA 7
150			#define VCR 1
151			#define CAMERA 0
152
153			/*
154			* HUE/SATUATION REGISTER
155			*/
156			#define MSK_HUE 0xE0
157			#define SHF_HUE 0
158			#define MAX_HUE 0x1f
159
160			#define MSK_SATURATION 0x1F
161			#define SHF_SATURATION 5
162			#define MAX_SATURATION 0x07
163
164
165			/*
166			* *********************************************
167			* Display register settings
168			* *********************************************
169			*
170			* Screen Positioning Registers:
171			* DR 0-3
172			*/
173			#define LEFTBORDER 0
174			#define DEF_LEFT 85
175			#define MIN_LEFT 75
176			#define MAX_LEFT 95
177			#define RIGHTBORDER 1
178			#define DEF_RIGHT (DEF_LEFT+256)
179			#define TOPBORDER 2
180			#define DEF_TOP 40
181			#define MIN_TOP 20
182			#define BOTTOMBORDER 3
183			#define DEF_BOTTOM (DEFTOP+DEFROWS/2)
184			#define MAX_BOTTOM 261
185
186			/*
187			* REgisters which track 0-3
188			*/
189			#define DR8 8
190			#define PRESHIFT DR8
191			#define EQU_DR8 DR0
192			#define DR9 9
193			#define EQU_DR9 DR1
194			#define DR10 10
195			#define EQU_DR10 DR2
196			#define DR11 11
197			#define EQU_DR11 DR3
198
199			/*
200			* REQUIRED REGISTERS
201			*/
202			#define DR4 4
203			#define DEF_DR4 352
204			#define DR5 5
205			#define DEF_DR5 1
206			#define DR6 6
207			#define DEF_DR6 0
208			#define DR7 7
209			#define DEF_DR7 511
210			#define DR12 12
211			#define DEF_DR12 20
212			#define DR13 13
213			#define DEF_DR13 22
214			#define DR14 14
215			#define DEF_DR14 0
216			#define DR15 15
217			#define DEF_DR15 511
218			#define DR16 16
219			#define DEF_DR16 0
220			#define DR17 17
221			#define DEF_DR17 0
222			#define DR18 18
223			#define DEF_DR18 0
224			#define DR19 19
225			#define DEF_DR19 4
226
227			/* interlace mode register & parameters */
228			#define DR20 20
229			#define INTREG 0x14
230			#define DEF_INT 0 /* default to interlace mode 0 */
231			#define MSK_INTERLACE 0x0003
232
233
234
235			struct TARStruct {
236			/* Board Configuration */
237			int memloc; /* memory segment */
238			int iobase; /* IOBASE segment */
239			int BytesPerPixel; /* number of words per pixel */
240			int RowsPerBank; /* number of row per 64K bank */
241			int MaxBanks; /* maximum bank id */
242			int AddressShift; /* number of bits to shift address */
243
244			/* Control registers */
245			int mode; /* mode register */
246			int Mask; /* mask register */
247			int PageMode; /* current page mode (screen res. and page) */
248			unsigned PageLower; /* Lower Page Select register */
249			unsigned PageUpper; /* upper Page select register */
250			int VCRCon; /* VCRContract register */
251			int SatHue; /* Hue and Saturation register */
252			long BorderColor; /* Border color register */
253			int VertShift; /* Vertical Pan Register */
254
255			int PanXOrig, PanYOrig; /* x,y pan origin */
256
257			/* TARGA-SET PARAMETERS */
258			int boardType; /* See TYPE_XX IN THIS FILE */
259			/* FOR DEFINITION OF Board Types */
260			int xOffset; /* X-offset */
261			int yOffset; /* Y-Offset */
262			int LinesPerField; /* maximum visible row count */
263			int InterlaceMode; /* desired interlace mode */
264			int AlwaysGenLock; /* Genlock always on or not */
265			int Contrast; /* Desired Contrast */
266			int Hue; /* Desired Hue */
267			int Saturation; /* Desired Satuation */
268			int RGBorCV; /* CV or RGB Input */
269			int VCRorCamera; /* VCR or Camera */
270			int ovrscnAvail, ovrscnOn; /* ovrscnAvail 1 if Overscan installed */
271			/* ovrscnOn 1 if overscan is stretching */
272
273			/* Display Registers */
274			int DisplayRegister[22];
275			};
276
277			struct M8Struct {
278			int there; /* flag to indicate if m8 is present */
279			/* logical true if M8 present (i.e. 1) */
280			/* and logical false (0) otherwise */
281			int inOffset; /* input offset */
282			int inGain; /* input gain */
283			int inputMux; /* input channel */
284			int modeRegister; /* value of the mode register on the M8 top */
285			int inMap, outMap; /* active input/output color map */
286			int loopThru; /* logical flag if M8 loop-through is desired */
287			/* of CGA input 1---YES, 0---No */
288			int topFunction; /* currently selected top function */
289			int CGAInterlace; /* interlace mode for a CGA if used */
290			};
291
292			#define M8MODE 0x400 /* IO Offset for writes to M8 Mode register */
293			#define M8WRITE 0x402 /* Offset for writes to M8 function registers */
294			#define M8READ 0x802 /* Offset for reads from M8 function registers */
295
296			#define DEF_M8MODE 2
297			#define DEF_M8GAIN 50
298			#define DEF_M8OFFSET 50
299			#define DEF_M8MUX 0
300			#define DEF_M8INMAP 0
301			#define DEF_M8OUTMAP 0
302			#define DEF_CGAINTERLACE 3
303
304
305			struct hdStruct {
306			char textSize;
307			char mapType;
308			char dataType;
309			int mapOrig;
310			int mapLength;
311			char CMapBits;
312			int XOffset;
313			int YOffset;
314			int x;
315			int y;
316			int dataBits, imType;
317			} ;
318
319
320			/* stroke font file */
321
322			typedef struct{
323			int width; /* width of character */
324			int height; /* height of char from baseline */
325			int descent; /* descent below baseline */
326			int index; /* index into stroke table */
327			} SFONTCHAR;
328
329			typedef struct {
330			int dx; /* dx of character */
331			int dy; /* dy of character */
332			int dd; /* dy of descenders */
333			int first; /* value of first char in font */
334			int last; /* value of last char in font */
335			int strokes; / where the strokes are located */
336			SFONTCHAR info; / info on each character */
337			} SFONT;